1. Field of the Invention
The present invention relates generally to a semiconductor device such as a large scale integrated circuit device (LSI), etc., and more specifically to a semiconductor device including complementary insulating gate field effect transistors and bipolar transistors in a chip (semiconductor substrate). The present invention is especially applicable to a semiconductor device of a so-called Bi-COMS (Bipolar-Complementary Metal Oxide Semiconductor) type. The present invention also relates to the manufacturing method of such a semiconductor device.
2. Description of the Background Art
The present invention brings about the most preferable effects when applied to an LSI including CMOS transistors along with bipolar transistors in a chip, i.e. a so-called Bi-CMOS type semiconductor device. FIGS. 24 to 29 are sectional views showing the manufacturing method of a conventional Bi-CMOS type semiconductor device in the manufacturing order. The structure of the Bi-CMOS type semiconductor substrate and the manufacturing method thereof will be described in conjunction with these figures.
Referring to FIG. 24, a silicon oxide film is formed on a p type silicon semiconductor substrate 1 by, for example, thermal oxidation, etc. The silicon oxide film is patterned to form silicon oxide films 2a, 2b, and 2c, which expose prescribed regions. Using silicon oxide films 2a, 2b, and 2c as masks, an N type impurity such as antimony (Sb), etc. is introduced into p type silicon semiconductor substrate 1 by means of ion implantation, etc. and is diffused. N.sup.+ diffusion layers 3 and 5 are thus formed at one time.
Now, referring to FIG. 25, silicon oxide film 2a, 2b, and 2c are removed. Then a silicon oxide film 6 is once again formed entirely on p type silicon semiconductor substrate 1. A photoresist film is formed on silicon oxide film 6. The photoresist film is patterned to form photoresist films 7a and 7b to expose only a prescribed surface region of silicon oxide film 6. Using photoresist films 7a and 7b as masks, a p type impurity such as boron (B), etc. is introduced into p type silicon semiconductor substrate 1 and is diffused. A p.sup.+ diffusion layer 8 is thus formed.
Thereafter, photoresist films 7a and 7b, and silicon oxide film 6 are sequentially removed as shown in FIG. 26.
As shown in FIG. 27, epitaxial growth is performed to grow a silicon layer entirely on p type silicon semiconductor substrate 1. An epitaxial layer 9 having a thickness of approximately 2 .mu.m is thus formed. At that time, n.sup.+ diffusion layers 3 and 5, and a p.sup.+ diffusion layer 8 become n.sup.+ buried layers 3a and 5a, and a p.sup.+ buried layer 8a by the process of thermal treatment during the process of the epitaxial growth.
Referring to FIG. 28, an n type impurity such as phosphorus is, for example, introduced into epitaxial layer 9 above n.sup.+ buried layers 3a and 5a by ion implantation, etc.. The diffusion of the n type impurity permits n.sup.- well regions 10 and 12 to be formed above n.sup.+ buried layers 3a and 5a, respectively. A p type impurity such as boron (B) is introduced into epitaxial layer 9 above p.sup.+ buried layer 8a by ion implantation, etc.. The diffusion of the p type impurity permits p.sup.- well region 11 to be formed above p.sup.+ buried layer 8a. After these n.sup.- regions 10, 12 and p.sup.- well region 11 are sequentially formed, oxide films for element isolation 13a to 13e are formed for example by means of LOCOS (Local Oxidation of Silicon).
Finally, as shown in FIG. 29, an n type impurity such as phosphorus (P) is diffused in a region between oxide films for element isolation 13a and 13b, thereby forming an n.sup.+ diffusion layer for conducting a collector 14. Sequentially formed thereafter are the elements of MOS transistors: gate oxide films 15a and 15b; gate electrodes 16a and 16b; n.sup.+ source/drain diffusion layers 17a and 17b; and p.sup.+ source/drain diffusion layers 18a and 18b;, and the elements of bipolar transistors: a p.sup.+ diffusion layer 18c for conducting a base; a p.sup.- intrinsic base region 19; and an n.sup.+ emitter region 20.
As described above, an npn bipolar transistor 21, an n channel MOS transistor 22, a p channel MOS transistor 23 are formed, which constitute a Bi-CMOS type semiconductor device as a whole.
As shown in FIG. 24, n.sup.+ buried layer 3a is formed by implantation of antimony, in which npn bipolar transistor 21 is formed, the background of which will be described in the following.
It is conventionally known that reducing the size of a bipolar transistor according to the scaling law brings about cost reduction due to increase in the integration density as well as improvement in the operating speed of the transistor due to reduction in parasitic capacitance, parasitic resistance and carrier running time. It has been apparent that as the thickness of, for example, a silicon epitaxial layer is reduced according to the scaling law, f.sub.T (cut-off frequency) which is an indicator of high speed operation achieved by the bipolar transistor increases as shown in FIG. 30, but the collector-emitter breakdown voltage BV.sub.CEO is tremendously degraded.
The thickness of a silicon epitaxial layer is scaled to as thick as 2 .mu.m and less, and it is a major issue how to secure BV.sub.CEO while achieving high speed operation of a bipolar transistor.
The following two approaches are possible for securing the BV.sub.CEO.
(i) In the conventional Bi-CMOS type semiconductor device shown in FIG. 29, for example, the impurity concentration of intrinsic base region 19 in npn bipolar transistor 21 is increased.
(ii) In the conventional Bi-CMOS type semiconductor device shown in FIG. 29, the impurity concentration of n.sup.- well region 10 is reduced while restraining the rising of n.sup.+ buried layer 3a onto the side of epitaxial layer 9 due to auto doping as much as possible. The impurity concentration of n.sup.+ buried layer 3a itself should be increased as much as possible for the purpose of reducing the parasitic resistance.
The term "auto doping" refers to the phenomenon in which an impurity in a substrate once jumps into vapor phase during the growth of epitaxial layer 9 and is once again taken up into the epitaxial layer. For example, FIG. 31 illustrates the impurity concentration profile of a typical npn bipolar transistor in its depthwise direction, and it can be understood from this figure that a gentle slope Q is produced on the side of the epitaxial layer (epi layer) in the impurity concentration profile of the n.sup.+ buried layer.
More specifically, the auto doping phenomenon is essentially different from so-called outward diffusion in which an impurity diffuses directly from a substrate during epitaxial growth.
In the case of (i), increase of the impurity concentration of intrinsic base region 19 results in great degradation in the current amplification factor h.sub.FE which is one important characteristic of a bipolar transistor. This is because h.sub.FE which is approximately represented by the equation: EQU h.sub.FE =N.sub.E /(N.sub.B .multidot.W.sub.B)
(where N.sub.E is emitter concentration, N.sub.B is base concentration, and W.sub.B is base width) is degraded when the base concentration N.sub.B increases.
As a result, it is difficult to maintain h.sub.FE at a level around 100 possessed by a general bipolar transistor and the approach of (i) can hardly be reduced to practice.
In the case of (ii), too much reduction in the impurity concentration of n.sup.- well region 10 results in the diffusion of the impurity forming p.sup.- intrinsic base region 19, increases the base width W.sub.B and degrades h.sub.FE as in the above-stated equation representing h.sub.FE or f.sub.T is degraded by increase of the base running time, thereby hindering high speed operation of the transistor. Consequently, the impurity concentration of n.sup.- well region 10 can only be reduced to somewhere around 10.sup.16 /cm.sup.3 in practice.
It is therefore necessary to use an impurity less subject to auto doping in order to restrain the rising of n.sup.+ buried layer 3a onto the side of epitaxial layer 9 due to the auto doping as much as possible.
FIG. 32 is a graphic representation showing the temperature dependence of the diffusion coefficients of n type impurities, phosphorus (P), arsenic (As) and antimony (Sb) in the silicon. According to FIG. 32, the relation between the diffusion coefficients in the silicon in a prescribed temperature range is represented as phosphorus (P)&gt;antimony (Sb)&gt;arsenic (As). Unlike outward diffusion, the auto doping does not depend on the diffusion coefficients themselves as shown in FIG. 32. The auto doping varies with the conditions of silicon epitaxial growth, specially the kind of dopant used, and the relation between the coefficients of n type impurities is represented as phosphorus (P)&gt;arsenic (As)&gt;&gt;antimony (Sb).
For the reasons stated above, antimony (Sb) is used for forming n.sup.+ buried layer 3a with the impurity concentration of n.sup.- well region 10 being approximately 10.sup.16 /cm.sup.3, in order to achieve high speed operation of the bipolar transistor while securing BV.sub.CEO by scaling the silicon epitaxial layer.
In the usual manufacture of Bi-CMOS type semiconductor devices, n.sup.- well region 10 as the region in which npn bipolar transistor 21 is to be formed is formed as shown in FIG. 28 simultaneously with and having the same impurity concentration as n.sup.- well region 12 as the region in which p channel MOS transistor 23 is to be formed. Also, as can be seen from FIGS. 24 and 27, n.sup.+ buried layer 3a in which npn bipolar transistor 21 is to be formed is formed simultaneously with and having the same impurity concentration as n.sup.+ buried layer 5a in which p channel MOS transistor 23 is to be formed.
Therefore, if the impurity concentration of n.sup.- well region 10 is reduced to 10.sup.16 /cm.sup.3 for preventing deterioration in the bipolar transistor performance, and antimony (Sb) is used as an impurity for the formation of n.sup.+ buried layer 3a as described above, the impurity concentration of n.sup.- well region 12 on which p channel MOS transistor 23 is to be formed will be reduced to 10.sup.16 /cm.sup.3 as well. This causes the drain depletion layer in the p channel MOS transistor to be easily expanded, thereby facilitating the formation of a punch through between source/drain. "Punch through" means a phenomenon in which a drain depletion layer extends close to a source, the drain depletion layer and the source depletion layer are connected with each other and therefore the electric field in the drain has an effect on the source side, resulting in the drop of the diffusion potential between source well, so that current flows between the source-drain without the formation of a channel. An approach for preventing only the formation of this punch through phenomenon has been proposed by the present inventors et al in Japanese Patent Laying-Open No. 2-106961, which discloses the keeping of the impurity concentration higher in n.sup.- well region 10 on which the p channel MOS transistor is to be formed than in n.sup.- well region 10.
Also as shown in FIG. 29, n.sup.+ buried layer 3a to be used as the collector of the bipolar transistor has preferably its resistance kept low i.e. its concentration kept higher as described above. If antimony (Sb) is used as an impurity in the formation of n.sup.+ buried layer 3a, there is a limit to its high concentration. FIG. 33 is a graphic representation showing the solid solubilities of Arsenic (As), phosphorus (P), and antimony (Sb) into silicon. As shown in FIG. 33, the solid solubility of antimony (Sb) into silicon is lower than those of the other n type impurities arsenic (As) and phosphorus (P). The highest concentration of n.sup.+ buried layer 3a formed using antimony (Sb) in practice is therefore only about 10.sup.19 /cm.sup.3. The formation of p channel MOS transistor in n.sup.- well region 12 having a concentration as low as the above-described 10.sup.16 /cm.sup.3 makes it difficult to improve the latch up tolerance of a complementary MOS transistor.
Here, the term "latch up" indicates a phenomenon in which pnp and npn parasitic bipolar transistors are formed in a complementary MOS transistor, constituting a thyristor of pnpn between a power supply potential (V.sub.DD) and a ground potential GND (V.sub.SS), and once an extraneous noise is applied, current continues to flow between V.sub.DD and GND, resulting in breakdown.
FIG. 34 is a sectional view schematically showing one example of a parasitic thyristor formed in complementary MOS transistors in a Bi-CMOS type semiconductor device similar to the one illustrated by referring to FIG. 29. In FIG. 34, if the impurity concentrations of an n.sup.+ buried layer and a p.sup.+ buried layer are low, voltage drops (voltage drops corresponding to resistances Rn, Rp) become larger when a surge noise is applied and current flows through these buried layers. This causes the emitter-bases of a parasitic pnp bipolar transistor Q1 and a parasitic npn bipolar transistor Q2 to be biased. As a result, these parasitic transistors are operated, and, therefore, the above-described latch up phenomenon is more likely to happen.
Among other prior art devices, a semiconductor device is disclosed in Japanese Patent Laying-Open No. 64-82648, in which the depth to a buried layer in a bipolar transistor region is made shorter than the depth to a buried layer in an MOS transistor region. In the semiconductor device, as the thickness of an epitaxial layer is reduced in accordance with the scaling law, it becomes difficult to secure a breakdown voltage VB.sub.CEO. In contrast, it will be necessary to increase the impurity concentration of a base region as described above for securing the breakdown voltage VB.sub.CEO. The increase in the impurity concentration of the base region causes the current amplification factor h.sub.FE of the bipolar transistor to be decreased as described above. Consequently, it will be hard to maintain the bipolar transistor with a high performance.
Furthermore, Japanese Patent Laying-Open No. 1-259554 discloses a manufacturing method of a semiconductor device which uses impurities having different diffusion coefficients for forming the buried layer of a bipolar transistor region and the buried layer of an MOS transistor region. In practice, however, the kind of impurity for forming a buried layer has little influence on the characteristics of a transistor to be formed thereon. The position as well as the impurity concentration of the buried layer have in fact a great effect on the performance of the transistor. If the impurity concentration of an n.sup.+ buried layer itself is low, the formation of the n.sup.+ buried layer using an impurity having a large diffusion coefficient and the reduction of the region between the n.sup.+ buried layer and a p.sup.- base layer in a region for forming a bipolar transistor can instead give rise to other problems such as a large collector resistance. It is therefore difficult to maintain the performance of the bipolar transistor without taking into account the impurity concentration of the buried layer.